Japanese Patent Application No. 2000-320977, filed on Oct. 20, 2000, is hereby incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device which holds data by refreshing, a method of refreshing the semiconductor device, a memory system, and an electronic instrument.
2. Description of Related Art
A virtually static RAM (VSRAM) is one type of semiconductor memory. Although memory cells of the VSRAM are the same as memory cells of a DRAM, the VSRAM does not need multiplexing of the column address and the row address. Moreover, the user can use the VSRAM without taking refreshing into consideration (transparency of refreshing).
A certain type of VSRAM is operated in two or more operating states such as a normal operating state and a power saving state. In such a VSRAM, sufficient consideration is not given to internal refreshing performed in each operating state. This problem is not limited to the VSRAM, but is common to dynamic type semiconductor memory devices having a built-in refresh timer and refresh control sections.
The present invention has been achieved to overcome the above conventional problem. An objective of the present invention is to provide a technique capable of performing refresh operations suitable for a plurality of operating states of a semiconductor memory device.
(1) According to a first aspect of the present invention, there is provided a method of refreshing a semiconductor device having a memory cell array divided into a plurality of blocks, the method comprising:
a first step of making the semiconductor device externally accessible;
a second step of refreshing a block other than a block to be externally accessed among the plurality of blocks of the memory cell array when the semiconductor device is in an externally accessible state;
a third step of making the semiconductor device externally inaccessible; and
a fourth step of refreshing only part of the memory cell array when the semiconductor device is in an externally inaccessible state.
(2) A second aspect of the present invention provides a semiconductor device which holds data by refreshing, comprising:
a memory cell array divided into a plurality of blocks;
a refresh address signal generation circuit which generates a first refresh address signal formed of a plurality of signals and is used to select a memory cell to be refreshed in each of the blocks;
a refresh address signal control circuit which generates a second refresh address signal in which logic of part of the signals forming the refresh address signal is made constant in an externally inaccessible state; and
a refresh control circuit which refreshes a memory cell in a block other than a block to be externally accessed among the plurality of blocks, based on the first refresh address signal in an externally accessible state of the semiconductor device, and also refreshes a memory cell in each of the blocks, based on the second refresh address signal in the externally inaccessible state.
(3) A third aspect of the present invention provides a memory system comprising the semiconductor device as defined in the above (2).
(4) A fourth aspect of the present invention provides an electronic instrument comprising the semiconductor device as defined in the above (2).